mirror of
https://github.com/emsesp/EMS-ESP32.git
synced 2025-12-07 16:29:51 +03:00
replace OneWire
This commit is contained in:
MichaelDvP
@@ -1,16 +1,14 @@
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#ifndef OneWire_h
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#define OneWire_h
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#ifdef __cplusplus
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#include <stdint.h>
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#include <inttypes.h>
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#if defined(__AVR__)
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#include <util/crc16.h>
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#endif
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#if ARDUINO >= 100
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#include <Arduino.h> // for delayMicroseconds, digitalPinToBitMask, etc
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#include "Arduino.h" // for delayMicroseconds, digitalPinToBitMask, etc
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#else
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#include "WProgram.h" // for delayMicroseconds
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#include "pins_arduino.h" // for digitalPinToBitMask, etc
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@@ -42,7 +40,7 @@
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// old versions of OneWire). If you disable this, a slower
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// but very compact algorithm is used.
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#ifndef ONEWIRE_CRC8_TABLE
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#define ONEWIRE_CRC8_TABLE 1
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#define ONEWIRE_CRC8_TABLE 0
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#endif
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// You can allow 16-bit CRC checks by defining this to 1
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@@ -51,8 +49,388 @@
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#define ONEWIRE_CRC16 1
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#endif
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// Board-specific macros for direct GPIO
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#include "OneWire_direct_regtype.h"
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef TRUE
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#define TRUE 1
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#endif
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// Platform specific I/O definitions
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#if defined(__AVR__)
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#define PIN_TO_BASEREG(pin) (portInputRegister(digitalPinToPort(pin)))
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#define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin))
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#define IO_REG_TYPE uint8_t
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#define IO_REG_BASE_ATTR asm("r30")
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#define IO_REG_MASK_ATTR
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#define DIRECT_READ(base, mask) (((*(base)) & (mask)) ? 1 : 0)
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#define DIRECT_MODE_INPUT(base, mask) ((*((base) + 1)) &= ~(mask))
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#define DIRECT_MODE_OUTPUT(base, mask) ((*((base) + 1)) |= (mask))
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#define DIRECT_WRITE_LOW(base, mask) ((*((base) + 2)) &= ~(mask))
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#define DIRECT_WRITE_HIGH(base, mask) ((*((base) + 2)) |= (mask))
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#elif defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__) || defined(__MK64FX512__)
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#define PIN_TO_BASEREG(pin) (portOutputRegister(pin))
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#define PIN_TO_BITMASK(pin) (1)
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#define IO_REG_TYPE uint8_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR __attribute__((unused))
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#define DIRECT_READ(base, mask) (*((base) + 512))
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#define DIRECT_MODE_INPUT(base, mask) (*((base) + 640) = 0)
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#define DIRECT_MODE_OUTPUT(base, mask) (*((base) + 640) = 1)
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#define DIRECT_WRITE_LOW(base, mask) (*((base) + 256) = 1)
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#define DIRECT_WRITE_HIGH(base, mask) (*((base) + 128) = 1)
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#elif defined(__MKL26Z64__)
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#define PIN_TO_BASEREG(pin) (portOutputRegister(pin))
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#define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin))
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#define IO_REG_TYPE uint8_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR
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#define DIRECT_READ(base, mask) ((*((base) + 16) & (mask)) ? 1 : 0)
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#define DIRECT_MODE_INPUT(base, mask) (*((base) + 20) &= ~(mask))
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#define DIRECT_MODE_OUTPUT(base, mask) (*((base) + 20) |= (mask))
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#define DIRECT_WRITE_LOW(base, mask) (*((base) + 8) = (mask))
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#define DIRECT_WRITE_HIGH(base, mask) (*((base) + 4) = (mask))
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#elif defined(__SAM3X8E__) || defined(__SAM3A8C__) || defined(__SAM3A4C__)
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// Arduino 1.5.1 may have a bug in delayMicroseconds() on Arduino Due.
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// http://arduino.cc/forum/index.php/topic,141030.msg1076268.html#msg1076268
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// If you have trouble with OneWire on Arduino Due, please check the
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// status of delayMicroseconds() before reporting a bug in OneWire!
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#define PIN_TO_BASEREG(pin) (&(digitalPinToPort(pin)->PIO_PER))
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#define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin))
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#define IO_REG_TYPE uint32_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR
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#define DIRECT_READ(base, mask) (((*((base) + 15)) & (mask)) ? 1 : 0)
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#define DIRECT_MODE_INPUT(base, mask) ((*((base) + 5)) = (mask))
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#define DIRECT_MODE_OUTPUT(base, mask) ((*((base) + 4)) = (mask))
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#define DIRECT_WRITE_LOW(base, mask) ((*((base) + 13)) = (mask))
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#define DIRECT_WRITE_HIGH(base, mask) ((*((base) + 12)) = (mask))
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#ifndef PROGMEM
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#define PROGMEM
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#endif
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#ifndef pgm_read_byte
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#define pgm_read_byte(addr) (*(const uint8_t *)(addr))
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#endif
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#elif defined(__PIC32MX__)
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#define PIN_TO_BASEREG(pin) (portModeRegister(digitalPinToPort(pin)))
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#define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin))
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#define IO_REG_TYPE uint32_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR
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#define DIRECT_READ(base, mask) (((*(base + 4)) & (mask)) ? 1 : 0) //PORTX + 0x10
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#define DIRECT_MODE_INPUT(base, mask) ((*(base + 2)) = (mask)) //TRISXSET + 0x08
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#define DIRECT_MODE_OUTPUT(base, mask) ((*(base + 1)) = (mask)) //TRISXCLR + 0x04
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#define DIRECT_WRITE_LOW(base, mask) ((*(base + 8 + 1)) = (mask)) //LATXCLR + 0x24
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#define DIRECT_WRITE_HIGH(base, mask) ((*(base + 8 + 2)) = (mask)) //LATXSET + 0x28
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#elif defined(ARDUINO_ARCH_ESP8266)
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// Special note: I depend on the ESP community to maintain these definitions and
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// submit good pull requests. I can not answer any ESP questions or help you
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// resolve any problems related to ESP chips. Please do not contact me and please
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// DO NOT CREATE GITHUB ISSUES for ESP support. All ESP questions must be asked
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// on ESP community forums.
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#define PIN_TO_BASEREG(pin) ((volatile uint32_t *)GPO)
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#define PIN_TO_BITMASK(pin) (1 << pin)
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#define IO_REG_TYPE uint32_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR
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#define DIRECT_READ(base, mask) ((GPI & (mask)) ? 1 : 0) //GPIO_IN_ADDRESS
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#define DIRECT_MODE_INPUT(base, mask) (GPE &= ~(mask)) //GPIO_ENABLE_W1TC_ADDRESS
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#define DIRECT_MODE_OUTPUT(base, mask) (GPE |= (mask)) //GPIO_ENABLE_W1TS_ADDRESS
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#define DIRECT_WRITE_LOW(base, mask) (GPOC = (mask)) //GPIO_OUT_W1TC_ADDRESS
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#define DIRECT_WRITE_HIGH(base, mask) (GPOS = (mask)) //GPIO_OUT_W1TS_ADDRESS
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#elif defined(ARDUINO_ARCH_ESP32)
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#include <driver/rtc_io.h>
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#define PIN_TO_BASEREG(pin) (0)
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#define PIN_TO_BITMASK(pin) (pin)
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#define IO_REG_TYPE uint32_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR
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static inline __attribute__((always_inline)) IO_REG_TYPE directRead(IO_REG_TYPE pin) {
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#if CONFIG_IDF_TARGET_ESP32C3
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return (GPIO.in.val >> pin) & 0x1;
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#else // plain ESP32
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if (pin < 32)
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return (GPIO.in >> pin) & 0x1;
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else if (pin < 46)
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return (GPIO.in1.val >> (pin - 32)) & 0x1;
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#endif
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return 0;
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}
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static inline __attribute__((always_inline)) void directWriteLow(IO_REG_TYPE pin) {
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#if CONFIG_IDF_TARGET_ESP32C3
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GPIO.out_w1tc.val = ((uint32_t)1 << pin);
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#else // plain ESP32
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if (pin < 32)
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GPIO.out_w1tc = ((uint32_t)1 << pin);
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else if (pin < 46)
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GPIO.out1_w1tc.val = ((uint32_t)1 << (pin - 32));
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#endif
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}
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static inline __attribute__((always_inline)) void directWriteHigh(IO_REG_TYPE pin) {
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#if CONFIG_IDF_TARGET_ESP32C3
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GPIO.out_w1ts.val = ((uint32_t)1 << pin);
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#else // plain ESP32
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if (pin < 32)
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GPIO.out_w1ts = ((uint32_t)1 << pin);
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else if (pin < 46)
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GPIO.out1_w1ts.val = ((uint32_t)1 << (pin - 32));
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#endif
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}
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static inline __attribute__((always_inline)) void directModeInput(IO_REG_TYPE pin) {
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#if CONFIG_IDF_TARGET_ESP32C3
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GPIO.enable_w1tc.val = ((uint32_t)1 << (pin));
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#else
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if (digitalPinIsValid(pin)) {
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#if ESP_IDF_VERSION_MAJOR < 4 // IDF 3.x ESP32/PICO-D4
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uint32_t rtc_reg(rtc_gpio_desc[pin].reg);
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if (rtc_reg) // RTC pins PULL settings
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{
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ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].mux);
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ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].pullup | rtc_gpio_desc[pin].pulldown);
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}
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//#elif ESP_IDF_VERSION_MAJOR > 3 // ESP32-S2 needs IDF 4.2 or later
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// int8_t rtc_io = esp32_gpioMux[pin].rtc;
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// uint32_t rtc_reg = (rtc_io != -1)?rtc_io_desc[rtc_io].reg:0;
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// if ( rtc_reg ) // RTC pins PULL settings
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// {
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// ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_io_desc[rtc_io].mux);
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// ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_io_desc[rtc_io].pullup | rtc_io_desc[rtc_io].pulldown);
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// }
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#endif
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// Input
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if (pin < 32)
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GPIO.enable_w1tc = ((uint32_t)1 << pin);
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else
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GPIO.enable1_w1tc.val = ((uint32_t)1 << (pin - 32));
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// uint32_t pinFunction((uint32_t)2 << FUN_DRV_S); // what are the drivers?
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// pinFunction |= FUN_IE; // input enable but required for output as well?
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// pinFunction |= ((uint32_t)PIN_FUNC_GPIO << MCU_SEL_S);
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// ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = pinFunction;
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// GPIO.pin[pin].val = 0;
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}
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#endif
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}
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static inline __attribute__((always_inline)) void directModeOutput(IO_REG_TYPE pin) {
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#if CONFIG_IDF_TARGET_ESP32C3
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GPIO.enable_w1ts.val = ((uint32_t)1 << (pin));
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#else
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if (digitalPinIsValid(pin) && pin <= 33) // pins above 33 can be only inputs
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{
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#if ESP_IDF_VERSION_MAJOR < 4 // IDF 3.x ESP32/PICO-D4
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uint32_t rtc_reg(rtc_gpio_desc[pin].reg);
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if (rtc_reg) // RTC pins PULL settings
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{
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ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].mux);
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ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].pullup | rtc_gpio_desc[pin].pulldown);
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}
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//#elif ESP_IDF_VERSION_MAJOR > 3 // ESP32-S2 needs IDF 4.2 or later
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// int8_t rtc_io = esp32_gpioMux[pin].rtc;
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// uint32_t rtc_reg = (rtc_io != -1)?rtc_io_desc[rtc_io].reg:0;
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// if ( rtc_reg ) // RTC pins PULL settings
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// {
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// ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_io_desc[rtc_io].mux);
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// ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_io_desc[rtc_io].pullup | rtc_io_desc[rtc_io].pulldown);
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// }
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#endif
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// Output
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if (pin < 32)
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GPIO.enable_w1ts = ((uint32_t)1 << pin);
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else // already validated to pins <= 33
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GPIO.enable1_w1ts.val = ((uint32_t)1 << (pin - 32));
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// uint32_t pinFunction((uint32_t)2 << FUN_DRV_S); // what are the drivers?
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// pinFunction |= FUN_IE; // input enable but required for output as well?
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// pinFunction |= ((uint32_t)PIN_FUNC_GPIO << MCU_SEL_S);
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// ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = pinFunction;
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// GPIO.pin[pin].val = 0;
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}
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#endif
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}
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#define DIRECT_READ(base, pin) directRead(pin)
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#define DIRECT_WRITE_LOW(base, pin) directWriteLow(pin)
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#define DIRECT_WRITE_HIGH(base, pin) directWriteHigh(pin)
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#define DIRECT_MODE_INPUT(base, pin) directModeInput(pin)
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#define DIRECT_MODE_OUTPUT(base, pin) directModeOutput(pin)
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//#warning "ESP32 OneWire testing"
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#elif defined(__SAMD21G18A__)
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#define PIN_TO_BASEREG(pin) portModeRegister(digitalPinToPort(pin))
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#define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin))
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#define IO_REG_TYPE uint32_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR
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#define DIRECT_READ(base, mask) (((*((base) + 8)) & (mask)) ? 1 : 0)
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#define DIRECT_MODE_INPUT(base, mask) ((*((base) + 1)) = (mask))
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#define DIRECT_MODE_OUTPUT(base, mask) ((*((base) + 2)) = (mask))
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#define DIRECT_WRITE_LOW(base, mask) ((*((base) + 5)) = (mask))
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#define DIRECT_WRITE_HIGH(base, mask) ((*((base) + 6)) = (mask))
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#elif defined(RBL_NRF51822)
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#define PIN_TO_BASEREG(pin) (0)
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#define PIN_TO_BITMASK(pin) (pin)
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#define IO_REG_TYPE uint32_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR
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#define DIRECT_READ(base, pin) nrf_gpio_pin_read(pin)
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#define DIRECT_WRITE_LOW(base, pin) nrf_gpio_pin_clear(pin)
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#define DIRECT_WRITE_HIGH(base, pin) nrf_gpio_pin_set(pin)
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#define DIRECT_MODE_INPUT(base, pin) nrf_gpio_cfg_input(pin, NRF_GPIO_PIN_NOPULL)
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#define DIRECT_MODE_OUTPUT(base, pin) nrf_gpio_cfg_output(pin)
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#elif defined(__arc__) /* Arduino101/Genuino101 specifics */
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#include "scss_registers.h"
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#include "portable.h"
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#include "avr/pgmspace.h"
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#define GPIO_ID(pin) (g_APinDescription[pin].ulGPIOId)
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#define GPIO_TYPE(pin) (g_APinDescription[pin].ulGPIOType)
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#define GPIO_BASE(pin) (g_APinDescription[pin].ulGPIOBase)
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#define DIR_OFFSET_SS 0x01
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#define DIR_OFFSET_SOC 0x04
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#define EXT_PORT_OFFSET_SS 0x0A
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#define EXT_PORT_OFFSET_SOC 0x50
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/* GPIO registers base address */
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#define PIN_TO_BASEREG(pin) ((volatile uint32_t *)g_APinDescription[pin].ulGPIOBase)
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#define PIN_TO_BITMASK(pin) pin
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#define IO_REG_TYPE uint32_t
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#define IO_REG_BASE_ATTR
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#define IO_REG_MASK_ATTR
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static inline __attribute__((always_inline)) IO_REG_TYPE directRead(volatile IO_REG_TYPE * base, IO_REG_TYPE pin) {
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IO_REG_TYPE ret;
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if (SS_GPIO == GPIO_TYPE(pin)) {
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ret = READ_ARC_REG(((IO_REG_TYPE)base + EXT_PORT_OFFSET_SS));
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} else {
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ret = MMIO_REG_VAL_FROM_BASE((IO_REG_TYPE)base, EXT_PORT_OFFSET_SOC);
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}
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return ((ret >> GPIO_ID(pin)) & 0x01);
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}
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static inline __attribute__((always_inline)) void directModeInput(volatile IO_REG_TYPE * base, IO_REG_TYPE pin) {
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if (SS_GPIO == GPIO_TYPE(pin)) {
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WRITE_ARC_REG(READ_ARC_REG((((IO_REG_TYPE)base) + DIR_OFFSET_SS)) & ~(0x01 << GPIO_ID(pin)), ((IO_REG_TYPE)(base) + DIR_OFFSET_SS));
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} else {
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MMIO_REG_VAL_FROM_BASE((IO_REG_TYPE)base, DIR_OFFSET_SOC) &= ~(0x01 << GPIO_ID(pin));
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}
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}
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static inline __attribute__((always_inline)) void directModeOutput(volatile IO_REG_TYPE * base, IO_REG_TYPE pin) {
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if (SS_GPIO == GPIO_TYPE(pin)) {
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WRITE_ARC_REG(READ_ARC_REG(((IO_REG_TYPE)(base) + DIR_OFFSET_SS)) | (0x01 << GPIO_ID(pin)), ((IO_REG_TYPE)(base) + DIR_OFFSET_SS));
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} else {
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MMIO_REG_VAL_FROM_BASE((IO_REG_TYPE)base, DIR_OFFSET_SOC) |= (0x01 << GPIO_ID(pin));
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}
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}
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static inline __attribute__((always_inline)) void directWriteLow(volatile IO_REG_TYPE * base, IO_REG_TYPE pin) {
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if (SS_GPIO == GPIO_TYPE(pin)) {
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WRITE_ARC_REG(READ_ARC_REG(base) & ~(0x01 << GPIO_ID(pin)), base);
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} else {
|
||||
MMIO_REG_VAL(base) &= ~(0x01 << GPIO_ID(pin));
|
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}
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}
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static inline __attribute__((always_inline)) void directWriteHigh(volatile IO_REG_TYPE * base, IO_REG_TYPE pin) {
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if (SS_GPIO == GPIO_TYPE(pin)) {
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WRITE_ARC_REG(READ_ARC_REG(base) | (0x01 << GPIO_ID(pin)), base);
|
||||
} else {
|
||||
MMIO_REG_VAL(base) |= (0x01 << GPIO_ID(pin));
|
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}
|
||||
}
|
||||
|
||||
#define DIRECT_READ(base, pin) directRead(base, pin)
|
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#define DIRECT_MODE_INPUT(base, pin) directModeInput(base, pin)
|
||||
#define DIRECT_MODE_OUTPUT(base, pin) directModeOutput(base, pin)
|
||||
#define DIRECT_WRITE_LOW(base, pin) directWriteLow(base, pin)
|
||||
#define DIRECT_WRITE_HIGH(base, pin) directWriteHigh(base, pin)
|
||||
|
||||
#elif defined(__riscv)
|
||||
|
||||
/*
|
||||
* Tested on highfive1
|
||||
*
|
||||
* Stable results are achieved operating in the
|
||||
* two high speed modes of the highfive1. It
|
||||
* seems to be less reliable in slow mode.
|
||||
*/
|
||||
#define PIN_TO_BASEREG(pin) (0)
|
||||
#define PIN_TO_BITMASK(pin) digitalPinToBitMask(pin)
|
||||
#define IO_REG_TYPE uint32_t
|
||||
#define IO_REG_BASE_ATTR
|
||||
#define IO_REG_MASK_ATTR
|
||||
|
||||
static inline __attribute__((always_inline)) IO_REG_TYPE directRead(IO_REG_TYPE mask) {
|
||||
return ((GPIO_REG(GPIO_INPUT_VAL) & mask) != 0) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void directModeInput(IO_REG_TYPE mask) {
|
||||
GPIO_REG(GPIO_OUTPUT_XOR) &= ~mask;
|
||||
GPIO_REG(GPIO_IOF_EN) &= ~mask;
|
||||
|
||||
GPIO_REG(GPIO_INPUT_EN) |= mask;
|
||||
GPIO_REG(GPIO_OUTPUT_EN) &= ~mask;
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void directModeOutput(IO_REG_TYPE mask) {
|
||||
GPIO_REG(GPIO_OUTPUT_XOR) &= ~mask;
|
||||
GPIO_REG(GPIO_IOF_EN) &= ~mask;
|
||||
|
||||
GPIO_REG(GPIO_INPUT_EN) &= ~mask;
|
||||
GPIO_REG(GPIO_OUTPUT_EN) |= mask;
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void directWriteLow(IO_REG_TYPE mask) {
|
||||
GPIO_REG(GPIO_OUTPUT_VAL) &= ~mask;
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void directWriteHigh(IO_REG_TYPE mask) {
|
||||
GPIO_REG(GPIO_OUTPUT_VAL) |= mask;
|
||||
}
|
||||
|
||||
#define DIRECT_READ(base, mask) directRead(mask)
|
||||
#define DIRECT_WRITE_LOW(base, mask) directWriteLow(mask)
|
||||
#define DIRECT_WRITE_HIGH(base, mask) directWriteHigh(mask)
|
||||
#define DIRECT_MODE_INPUT(base, mask) directModeInput(mask)
|
||||
#define DIRECT_MODE_OUTPUT(base, mask) directModeOutput(mask)
|
||||
|
||||
#else
|
||||
#define PIN_TO_BASEREG(pin) (0)
|
||||
#define PIN_TO_BITMASK(pin) (pin)
|
||||
#define IO_REG_TYPE unsigned int
|
||||
#define IO_REG_BASE_ATTR
|
||||
#define IO_REG_MASK_ATTR
|
||||
#define DIRECT_READ(base, pin) digitalRead(pin)
|
||||
#define DIRECT_WRITE_LOW(base, pin) digitalWrite(pin, LOW)
|
||||
#define DIRECT_WRITE_HIGH(base, pin) digitalWrite(pin, HIGH)
|
||||
#define DIRECT_MODE_INPUT(base, pin) pinMode(pin, INPUT)
|
||||
#define DIRECT_MODE_OUTPUT(base, pin) pinMode(pin, OUTPUT)
|
||||
#warning "OneWire. Fallback mode. Using API calls for pinMode,digitalRead and digitalWrite. Operation of this library is not guaranteed on this architecture."
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
class OneWire {
|
||||
private:
|
||||
@@ -64,7 +442,7 @@ class OneWire {
|
||||
unsigned char ROM_NO[8];
|
||||
uint8_t LastDiscrepancy;
|
||||
uint8_t LastFamilyDiscrepancy;
|
||||
bool LastDeviceFlag;
|
||||
uint8_t LastDeviceFlag;
|
||||
#endif
|
||||
|
||||
public:
|
||||
@@ -78,11 +456,7 @@ class OneWire {
|
||||
// Perform a 1-Wire reset cycle. Returns 1 if a device responds
|
||||
// with a presence pulse. Returns 0 if there is no device or the
|
||||
// bus is shorted or otherwise held low for more than 250uS
|
||||
#ifdef ARDUINO_ARCH_ESP32
|
||||
uint8_t IRAM_ATTR reset(void);
|
||||
#else
|
||||
uint8_t reset(void);
|
||||
#endif
|
||||
|
||||
// Issue a 1-Wire rom select command, you do the reset first.
|
||||
void select(const uint8_t rom[8]);
|
||||
@@ -105,18 +479,11 @@ class OneWire {
|
||||
|
||||
// Write a bit. The bus is always left powered at the end, see
|
||||
// note in write() about that.
|
||||
#ifdef ARDUINO_ARCH_ESP32
|
||||
void IRAM_ATTR write_bit(uint8_t v);
|
||||
#else
|
||||
void write_bit(uint8_t v);
|
||||
#endif
|
||||
void write_bit(uint8_t v);
|
||||
|
||||
// Read a bit.
|
||||
#ifdef ARDUINO_ARCH_ESP32
|
||||
uint8_t IRAM_ATTR read_bit(void);
|
||||
#else
|
||||
uint8_t read_bit(void);
|
||||
#endif
|
||||
|
||||
// Stop forcing power onto the bus. You only need to do this if
|
||||
// you used the 'power' flag to write() or used a write_bit() call
|
||||
// and aren't about to do another read or write. You would rather
|
||||
@@ -138,7 +505,7 @@ class OneWire {
|
||||
// might be a good idea to check the CRC to make sure you didn't
|
||||
// get garbage. The order is deterministic. You will always get
|
||||
// the same devices in the same order.
|
||||
bool search(uint8_t * newAddr, bool search_mode = true);
|
||||
uint8_t search(uint8_t * newAddr, bool search_mode = true);
|
||||
#endif
|
||||
|
||||
#if ONEWIRE_CRC
|
||||
@@ -186,10 +553,4 @@ class OneWire {
|
||||
#endif
|
||||
};
|
||||
|
||||
// Prevent this name from leaking into Arduino sketches
|
||||
#ifdef IO_REG_TYPE
|
||||
#undef IO_REG_TYPE
|
||||
#endif
|
||||
|
||||
#endif // __cplusplus
|
||||
#endif // OneWire_h
|
||||
Reference in New Issue
Block a user